System requirements needed to interact with and visualize large, time-dependent data sets include a large, high-bandwidth disk array to store the entire data set being processed, a high speed network to download a problem set, a large, high-speed memory to buffer all data required to process a single simulation time step, computational power that is adequate to manipulate, enhance, and visualize the data sets, and a real-time, high resolution visual display. Furthermore, it is important that these functions be provided within a highly programmable and flexible user environment.
One fundamental problem encountered in multiprocessor systems is the interconnection of a collection of processors and/or I/O devices to a common Global Memory. Typical shared bus solutions limit the number of devices that can be attached to the bus, as determined by the electrical characteristics of the bus interface logic and the total bandwidth limitation of the bus. Electrical factors which limit the maximum number of devices that can be supported on a shared bus include the total distributed capacitance, the loading presented by the attached interface logic, and bus termination logic relative to the maximum drive capability of the bus drivers. Factors limiting the total bandwidth of the shared bus include the operating clock speed and the width of the data paths.
Given the existing state of technology, known types of high-speed, shared buses typically limit the total number of bus loads (i.e., processor cards, memory cards, and I/O interface cards) to less than 20. Thus, assuming that each processor, I/O interface, and memory card represents one bus load, these multiprocessor systems are typically limited to less than ten processor nodes in order to support a complementary mix of memory and I/O devices.
It is one object of the invention to provide a Universal Buffered Interface (UBIF) for coupling multiple data processors, memory units, and I/O interfaces to a common high-speed interconnect, such as a shared system bus.
It is another object of the invention to provide a mechanism for one data processor of a multiprocessor system to rapidly communicate with any other data processor or group of data processors in the data processing system.